In digital transmission and communications, a wide variety of modulation schemes are used to encode data. For example, in a random NRZ data signal, data are represented by a constant signal level for the full duration of a bit interval, i.e., one clock cycle. By contrast, RZ (return-to-zero) data signals return to zero with each bit interval. In each case, all data transitions occur at clock transitions. However, not all clock transitions generate data transitions in NRZ data.
To decode the digital data under NRZ, RZ, or other modulation schemes, it is necessary, in general, to know the correct instances to sample the data. Preferably, the clock used to encode the data is available for decoding. However, in many cases, the encoding clock is not available, and a new clock must be synthesized at the receiving end.
However, it is sometimes desirable for system operators and system component manufacturers, who are not directly interested in the exact content of the data messages being sent and received, to know or monitor the frequency and phase behavior, both average and instantaneous, of the underlying clock of the data stream. Such measurements are particularly desirable in plesiosynchronous digital systems in which deliberate phase shifts are occasionally introduced to compensate for small clock frequency differences at different points of the system. Preferably, such measurements should be made in "live traffic", that is, made without interrupting the system operation. Furthermore, it is most desirable to make such measurements at relatively low speed, commensurate with the clock jitter bandwidth, in the presence of much higher data modulation bandwidth. For these measurements, it is not necessary to literally recover a physical clock.
Also, knowledge of the underlying clock frequency and phase can be used to monitor and control system performance and to predict bit error rate (BER), especially when the rate is too low for convenient measurement. Systems may be specified to tolerate a certain amount of jitter at various frequency components (jitter tolerance), and, therefore, the actual jitter at various system points should be measured (jitter generation). Jitter is considered as phase deviation above 10 Hz bandwidth. To guard against magnification of jitter when cascading components, the transfer of jitter from input to output should be characterized (jitter transfer). Ideally, these measurements are made during data modulation to be more realistic and, if possible, during actual system operation. When incompatibility does arise in system operation, a repeatable standard method of measurement is necessary to settle disputes between vendors and buyers, system operators, and service providers, as to whether each piece of equipment is within specifications, and, indeed, to determine if the specifications are adequate to ensure correct operation.
Although widely used, the conventional methods using phase lock loop (PLL) and surface acoustic wave (SAW) oscillators suffer from lack of accepted standards in PLL design regarding loop components, and loop dynamic filter and SAW detail performance parameters. In practice, the physical clocks synthesized likely differ from one design to another, even for identical data streams, thereby producing non-unique and non-repeatable measurements. This lack of repeatability is true even if the more serious PLL errors such as loss-of-lock or false locking have been overcome.
Therefore, persons skilled in the art would prefer a system for highly repeatable measurement based on an accurate representation of the underlying clock, independent of any particular circuit design detail or parametric performance of various components.